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PI6C2305-1
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3.3V Zero-Delay Buffer
Features
* Zero-input-output propagation delay * 350ps phase error * Multiple low-skew outputs - Output-output skew less than 250ps - Device-device skew less than 700ps * 10 MHz to 100 MHz operating range * Low Jitter <200ps * High drive option (PI6C2305-1H) * 3.3V operation * Commercial Operation: 0C to +70C * Industrial Operation: -40C to +85C * Package: Space-saving 8-pin, 150-mil SOIC package (W)
Description
Providing five low-skew clocks, the PI6C2305-1 is a 3.3V zero-delay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. The PI6C2305-1 provides 5 copies of clocks that have less than 350ps propagation delay compared to a reference clock. The skew among the output clock signals for PI6C2305-1 is less than 250ps. When there are no rising edges on the REF input, the PI6C2305-1 enters a power-down state. In this mode, the PLL is off and all outputs are three-stated. This results in less than 50A of current draw. Featuring faster rise and fall times, the PI6C2305-1H is the high-drive version of the PI6C2305-1.
Block Diagram
Pin Configuration
REF
FBK PLL
CLK0 CLK1 CLK2 CLK3 CLK4
REF CLK2 CLK1 GND
1 2 3 4
8-Pin W
8 7 6 5
CLK0 CLK4 VDD CLK3
Pin Description
Pin 1 2 3 4 5 6 7 8 Signal REF(1) CLK2(2) CLK1(2) GND CLK3
(2)
De s cription Input reference frequency, 5V Tolerant input Buffered Clock output Buffered Clock output Ground Buffered Clock output 3.3V Supply Buffered Clock output Buffered Clock output, internal feedback on this pin Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs.
VDD CLK4(2) CLK0(2)
1
PS9477A
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REF - Input to Output Clock Delay (ps)
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PI6C2305-1 3.3V Zero-Delay Buffer
Zero-Delay and Skew Control
REF. Input to CLK[1:4] Delay vs. Difference in Loading between CLK[0] pin and CLK[1:4] pins.
800
600
400
200
0 -25 -200 -20 -15 -10 -5 0 5 10 15 20 25
-400
PI6C2305-1H
-600
-800
PI6C2305-1
-900
-1000
Output Load Difference: CLK0 Load - CLK[1:4] Load (pF)
To achieve a Zero Delay between the input and output, all outputs should be uniformly loaded. The relative loading of CLK0 (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. For applications requiring zero input-output delay, all outputs including CLK0 should be equally loaded. Even if CLK0 is not used, it must have a capacitive load that is equal to that on every other output. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs.
Maximum Ratings
Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Input Voltage (Except REF) ............... -0.5V to VDD +0.5V DC Input Voltage REF .............................................. -0.5 to 7V Storage Temperature ..................................... -65 C to +150C Maximum Soldering Temperature (10 seconds) .............. 260C Junction Temperature ..................................................... 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ................................ >2000V
2
PS9477A
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Electrical Characteristics (Over operating conditions)
Parame te r VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD De s cription Input LOW Voltage(3) Input HIGH Voltage(3) Input LOW Current Input HIGH Current Output LOW Voltage(4) Output HIGH Voltage(4) VIN = 0V VIN = VDD IOL = 8mA (2305- 1) IOL = 12mA (2305- 1H) IOH = -8mA (2305- 1) IOH = -12mA (2305- 1H) REF = 0 MHz Unloaded outputs, 66.66 MHz, Te s t Conditions -- -- M in. -- 2.0 -- -- -- 2.4 -- -- M ax. 0.8 V -- 50.0 A 200.0 0.4 V -- 50.0 50.0 A mA Units
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PI6C2305-1 3.3V Zero-Delay Buffer
Operating Conditions
Parame te r VDD TA (2305, 2305- 1H) TA (2305I- 2305- 1HI) CL CIN De s cription Supply Voltage Commercial Temperature (Ambient) Industrial Temperature (Ambient) Load Capacitance Input Capacitance M in. 3 0 -40 M ax. 3.6 70 C 85 30 pF 7 Units V
Power Down Supply Current Supply Current
Notes: 3. REF and CLK0 inputs have a threshhold voltage of VDD/2. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
PS9477A
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2305-1 3.3V Zero-Delay Buffer
Switching Characteristics(4, 5) (Over operating conditions)
Parame te rs FCLK Name Output Frequency Duty Cycle(4) = t2 / t1 Duty Cycle(4) t3 t3 t4 t4 t5 t6 t7 t8 tJ tLOCK = t2 / t1 Te s t Conditions 30pF load Measured at VDD/2, FOUT < 66.66 MHz Measured at 1.4V, FOUT 45 MHz M in. 10 45 40 50 50 Typ. M ax. 100 55 % 60 2.5 Measured between 0.8V and 2.0V 1.5 ns 2.5 1.5 All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the output pins of devices Measured between 0.8V and 2.0V on - H device using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clocks presented on REFpins 1 200 1. 0 0 0 250 350 700 V/ns ps ms ps Units MHz
Rise Time(4) @30pF Rise Time(4)@30pF (H) Fall Time(4) @30pF Fall Time(4)@30pF (H) Output to Output Skew(4) Delay, REF Rising Edge to CLK0 Rising Edge(4) Device to Device Skew(4) Output Slew Rate(4) Cycle to Cycle Jitter(4) PLL Lock Time(4)
Notes: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. For definition of t1-8, see Switching Waveforms on page 5.
4
PS9477A
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PI6C2305-1 3.3V Zero-Delay Buffer
Switching Waveforms
Duty Cycle Timing
t1 t2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
3.3V
2.0V OUTPUT 0.8V
2.0V 0.8V 0V
t 3,t8
t 4,t8
Output-Output Skew
OUTPUT
1.4V
OUTPUT
1.4V
t5
Input-Output Propagation Delay
INPUT
VDD/2
VDD/2 CLK[1:4]
t6
Device-Device Skew
OUTPUT Device 1
VDD/2
OUTPUT Device 2
VDD/2
t7
Test Circuit #1
VDD
Test Circuit #2
VDD 1k
0.1F
OUTPUTS CLOAD VDD
0.1F
OUTPUTS 10pF
1k VDD
0.1F
GND
GND
0.1F
GND
GND
T est Circuit for all parameters except t 8
T est Circuit for
t 8 ,Output slew rate
on PI6C2305-1H device
5
PS9477A
06/06/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2305-1 3.3V Zero-Delay Buffer
8-Pin SOIC Package Mechanical (W)
8
.149 .157
3.78 3.99 .0099 .0196 0.25 x 45 0.50
1 .189 .196 4.80 5.00 0-8 .0075 .0098 0.40 .016 1.27 .050 .016 .026 0.406 0.660 REF .053 .068 1.35 1.75 SEATING PLANE .2284 .2440 5.80 6.20 0.19 0.25
.050 BSC 1.27 .013 0.330 .020 0.508
.0040 0.10 .0098 0.25
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Ordering Information
Orde ring Code PI6C2305- 1W PI6C2305- 1HW PI6C2305- 1WI PI6C2305- 1HWI De s cription Normal Drive 8- pin 150- mil SOIC High Drive Normal Drive 8- pin 150- mil SOIC High Drive Industrial Commercial Package Type Ope rating Range
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
6
PS9477A 06/06/00

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